The present invention relates to a method of manufacturing semiconductor devices, e.g., asymmetric MOS-type transistors and integrated circuits comprising such devices, with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention is also useful in the manufacture of asymmetric CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm and below.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires design features of 0.18 xcexcm and below, such as 0.15 xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called xe2x80x9cshort-channelxe2x80x9d effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly-doped source/drain extension type transistor structures have been developed, as described below.
For p-channel MOS transistors of short-channel type, the major limitation on performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch-throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped drain region is laterally displaced away from the gate by use of a sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
Several processing sequences or schemes have been developed for the manufacture of source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the requisite number of processing steps. Conventional processing schemes for making such MOS transistors generally employ disposable spacers made of various materials, e.g., polysilicon, silicon oxides, silicon nitrides, silicon oxynitrides, and combinations thereof.
According to one conventional process scheme, a precursor structure comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode formed on a portion of a surface thereof is subjected to ion implantation prior to sidewall spacer formation, for forming lightly- or moderately-doped implants therein. Following post-implantation annealing, sidewall spacers are formed on the pair of opposing side surfaces of the layer stack by first depositing a dielectric spacer material layer over the substrate surfaces and then removing same from the horizontally-oriented regions, i.e., the top surface of the gate electrode layer and the source and drain regions, by means of anisotropic etching. Such processing results in sidewall spacers left on the side surfaces of the gate layer stack that have an approximately quarter-circular shaped cross-section. The dielectric sidewall spacers typically remain through the balance of junction formation processing. After sidewall spacer formation, a heavy source/drain implantation is performed, with the gate layer stack and associated sidewall spacers acting as implantation masking materials. As a consequence of the separate implantations, the heavily-doped source/drain regions are laterally displaced from the gate edges by the thickness of the sidewall spacer material and the lightly- or moderately-doped regions beneath the sidewall spacers act as source/drain extensions.
According to another conventional process scheme, which scheme employs disposable (i.e., removable) sidewall spacers, a precursor structure as described above and comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode layer formed on a portion of a surface thereof is subjected to blanket-type dielectric layer deposition and patterning to form sidewall spacer layers on opposing side surfaces of the layer stack. Opposite conductivity type p- or n-type dopant impurities are then implanted into the substrate using the layer stack with sidewall spacers formed thereon as an implantation mask, to thereby form moderately- to heavily-doped implants. High temperature annealing is then performed to thermally activate the implanted dopant by diffusion and reduce lattice damage due to implantation, thereby forming source/drain regions and junctions at a predetermined density and depth below the substrate surface. The effective length of the channel of such transistors is determined by the width of the gate insulator/gate electrode layer stack and the width of the sidewall spacers formed thereon. After activation annealing, the sidewall spacers are removed, as by etching, and a second implantation process for implanting n- or p-type opposite conductivity type dopant impurities is performed using only the gate insulating layer/gate electrode layer stack as an implantation mask, thereby forming shallow-depth, lightly- or moderately-doped implants in the substrate in the spaces between the deeper, heavily-doped source/drain regions. Following this implantation, a second activation process, e.g., rapid thermal annealing (RTA), is performed for effecting dopant diffusion/activation and relaxation of implantation-induced lattice damage of the implants, to form shallow-depth, lightly- or moderately-doped source/drain extensions extending from respective proximal edges of the heavily-doped source/drain regions to just below the respective proximal edges of the gate insulator layer/gate electrode layer stack.
In a variant of the above-described process, the sidewall spacers are comprised of a layer of a first (or inner) dielectric material and a layer of a second (or outer) dielectric material. According to the process methodology of this variant, only the second, or outer, dielectric sidewall spacer layer is removed subsequent to annealing for forming the moderately- to heavily-doped source/drain regions. The first, or inner, dielectric sidewall spacer layer is retained for protecting the gate insulator/gate electrode layer stack during subsequent processing, e.g., for contact formation.
Each of the above-described variants employ removable sidewall spacers as part of an implantation mask for defining the channel lengths, and each incurs a drawback in that the materials conventionally used for the sidewall spacers, such as those enumerated above, frequently are difficult and time consuming to remove by standard etching methodologies, particularly when densified as a result of high temperature processing for post-implantation annealing for dopant activation/lattice damage relaxation. For example, and as described in U.S. Pat. No. 5,766,991, removal of silicon nitridebased spacer layers can require etching in a hot phosphoric acid (H3PO4) bath at about 180xc2x0 C. for approximately 1.5 hours. Such long etching time results in reduced manufacturing throughput and the extended exposure to and concomitant attack by the corrosive etchant at high temperature results in undesired etching and defect formation. Moreover, portions of the workpiece substrate not intended to be etched must be provided with an etch-resistant protective barrier layer, e.g., of silicon oxide, prior to etching. However, the etching resistance of the silicon oxide layer itself to the hot phosphoric acid may be insufficient, in which case the resistance thereof must be increased prior to etching, e.g., by first annealing it at about 900xc2x0 C. in an oxygen ambient. Alternatively, resistance to attack by the hot H3PO4 may be obtained by use of an oxide-polysilicon bi-layer. In either case, such requirement for provision of at least one layer for protecting from acid attack disadvantageously adds processing time, complexity, and fabrication cost. Etching of annealed, densified silicon oxide and/or silicon oxynitridebased sidewall spacer layers is similarly difficult.
Another approach towards alleviating or eliminating the problems of xe2x80x9cshort-channelxe2x80x9d effects in sub-micron dimensioned MOS transistors, such as the above-mentioned xe2x80x9chot carrierxe2x80x9d injection and xe2x80x9cpunch-throughxe2x80x9d phenomena, is the formation of xe2x80x9casymmetricxe2x80x9d source/drain structures, i.e., structures where the source and drain regions, including their associated lightly-doped, shallow-depth extensions, are not identically formed and constituted. For example, U.S. Pat. No. 5,510,279 issued Apr. 23, 1996, discloses a method of fabricating an asymmetric lightly doped drain transistor device, wherein the drain region is shielded with a barrier layer when ion implantation is conducted for implanting a highly doped source region. Following this implantation, a large angle implantation of opposite conductivity type dopant ions is performed for establishing a lightly doped xe2x80x9cpocketxe2x80x9d region adjacent the highly doped source region. The angled implantation which forms the pocket region increases the doping concentration along the device""s source side, thereby increasing the threshold voltage and, consequently diminishing xe2x80x9cshort-channelxe2x80x9d effects.
In another approach, disclosed in U.S. Pat. No. 5,811,338 issued Sep. 22, 1998, xe2x80x9cDIBLxe2x80x9d (i.e., Drain-Induced Barrier Lowering) and xe2x80x9chot electronxe2x80x9d short-channel effects in MOS transistors are alleviated by forming a second polarity internal junction region entirely within one of otherwise similar, first polarity source and drain regions. In yet another approach, disclosed in U.S. Pat. No. 5,547,885 issued Aug. 20, 1996, the widths of sidewall spacers on opposite side surfaces of gate insulator/gate electrode layer stacks are different; as a consequence thereof, the heavily doped source and drain regions, along with their respective shallow depth, lightly-doped extensions are of different lengths, resulting in formation of an asymmetric transistor structure wherein the hot carrier effect is suppressed by reducing peak field strength of a drain depletion layer caused by xe2x80x9cpinch-offxe2x80x9d.
A need exists for improved semiconductor manufacturing methodology for fabricating MOS and CMOS transistors exhibiting reduced short-channel effects such as are obtainable by formation of asymmetric structures as described above, by a process which employs removable spacer technology yet does not suffer from the above-described drawbacks associated with the difficulty in conveniently and rapidly removing densified sidewall spacers according to conventional etching techniques. Moreover, there exists a need for an improved process for fabricating asymmetrically-configured MOS transistor-based devices which is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-described problems and drawbacks attendant upon the application of conventional processing methodology for forming submicron-dimensioned, asymmetrically configured MOS and CMOS transistors for use in high-density semiconductor integrated circuit devices, particularly in providing a process utilizing a pair of removable dielectric sidewall spacer layers formed of a dielectric material, one of the pair being selectively subjected to a post-formation treatment for increasing the etchability thereof vis-a-vis that of its as-deposited state, wherein the treated spacer is readily removed by etching prior to a heavy ion implantation for defining heavily-doped source and drain regions, followed by thermal annealing treatment for dopant activation/lattice damage relaxation, which thermal annealing may disadvantageously density and thus increase the etching resistance of the spacer material. As a consequence of the selective removal of only one of the sidewall spacers, the heavy ion implantation results in asymmetric source/drain formation, i.e., the source or drain region formed at the side of the gate insulator/gate electrode layer stack from which the sidewall spacer has been removed is formed with its proximal edge reaching to just beneath the respective proximal edge of the gate insulator layer, whereas the source or drain region formed at the other side of the gate insulator/gate electrode layer stack having the sidewall spacer thereon is spaced-away therefrom by a distance approximately equal to the width of the spacer at its lower end adjacent the substrate surface. Following the heavy ion implantation, the remaining one of the sidewall spacers is removed by etching, and thermal annealing for diffusion/activation of the implanted dopant ions/atoms is performed. A second ion implantation is then performed for forming a shallow-depth, lightly-doped extension extending from the proximal edge of the spaced-away source or drain region to just beneath the respective proximal edge of the gate insulator layer. Relatively thin inner spacers formed of a dielectric material which is substantially less readily etched than the removable outer spacers are optionally provided on the opposing side surfaces of the gate insulator/gate electrode layer stack, which spacers are retained throughout processing for protecting the gate insulator/gate electrode layer stack from attack by corrosive atchant and during subsequent metallization for contact formation.
An advantage of the present invention is an improved method for manufacturing asymmetrically-configured MOS and/or CMOS transistor devices utilizing a removable spacer.
Another advantage of the present invention is an improved method for increasing the etchability of dielectric spacer materials utilized in the manufacture of asymmetrically-configured MOS, CMOS, and other types of semiconductor devices.
Yet another advantage of the present invention is an improved method for manufacturing asymmetrically-configured MOS and/or CMOS transistor devices utilizing a removable sidewall spacer formed of a readily etchable dielectric material.
Still another advantage of the present invention is an improved method of manufacturing submicron-dimensioned asymmetrically-configured MOS transistors for use in high-density semiconductor integrated circuit devices at lower cost, higher manufacturing throughput, and increased product yield and reliability than are obtainable with conventional process methodology.
Yet another advantage of the present invention is an improved asymmetrically-configured, submicron-dimensioned MOS transistor having a reduced amount of xe2x80x9cshort-channelxe2x80x9d effects.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises the sequential steps of:
(a) providing a device precursor structure comprising a semiconductor substrate of a first conductivity type and a layer stack formed on a portion of a surface of the substrate, the layer stack comprising:
i. a thin gate insulating layer in contact with the substrate surface; and
ii. a gate electrode layer formed on the gate insulating layer, the layer stack comprising first and second opposing side surfaces and a top surface;
(b) forming first and second insulative, tapered sidewall spacers on respective first and second opposing side surfaces of said layer stack, each of the sidewall spacers comprising a dielectric material having an as-deposited etch resistance;
(c) selectively positioning a masking material over the first sidewall spacer on the first opposing side surface of the layer stack;
(d) selectively treating the exposed second sidewall spacer on the second opposing side surface of the layer stack for reducing the etch resistance of the dielectric material from its as-deposited state to a more readily-etchable state;
(e) removing the masking material from over the first sidewall spacer;
(f) selectively removing the reduced etching resistance second sidewall spacer by an etching process;
(g) selectively introducing dopant impurities of a second, opposite conductivity type into exposed portions of the substrate surface adjacent the first sidewall spacer and adjacent the second opposing side surface of the layer stack to form a pair of spaced-apart, heavily-doped regions in the substrate;
(h) removing the first sidewall spacer by an etching process;
(i) thermally treating the pair of spaced-apart, heavily-doped regions to form a pair of heavily-doped source/drain regions in the substrate each having a junction therewith at a predetermined depth below the substrate surface, a first one of the pair of heavily-doped source/drain regions being laterally spaced away from a respective proximal edge of the gate insulating layer by a distance substantially equal to the width of the lower end of the first sidewall spacer adjacent the substrate surface and a second one of the pair of heavily-doped source/drain regions extending to just beneath a respective proximal edge of the gate insulating layer;
(j) selectively introducing second, opposite conductivity type dopant impurities into the exposed portion of the substrate surface intermediate the gate insulating layer and the first, laterally spaced-away, heavily-doped source/drain region to form a lightly- or moderately-doped extension region; and
(k) thermally treating the lightly- or moderately-doped extension region to form a shallow-depth, lightly- or moderately-doped source/drain extension in the substrate extending from a proximal edge of the first, laterally spaced-away, heavily-doped source/drain region to just beneath the respective proximal edge of the gate insulating layer.
In embodiments according to the present invention, step (a) comprises providing a silicon wafer substrate of n or p first conductivity type, the thin gate insulating layer comprises a silicon oxide layer about 25-50 xc3x85 thick, and the gate electrode layer comprises heavily-doped polysilicon; step (b) comprises forming the first and second sidewall spacers from a dielectric material having an as-deposited etch resistance and comprising a UV-nitride, each of the tapered sidewall spacers having a width profile varying from relatively wide at the lower end thereof adjacent the substrate surface to relatively narrow at the upper end thereof; step (c) comprises selectively forming a layer of photoresist over the first sidewall spacer or selectively positioning an ion implantation mask over the first sidewall spacer; step (d) comprises selective ion implantation of the second sidewall spacer, comprising selectively implanting impurity ions selected from Si+, Ge+, and p and n type dopant ions at preselected dosages and energies; step (f) comprises selectively removing the ion implanted, reduced etching resistance second insulative sidewall spacer by etching with dilute aqueous HF, e.g., 1:100 HF/H2O at about 20-35xc2x0 C.; step (g) comprises selectively implanting dopant ions of second, opposite conductivity type at dosages of from about 5xc3x971014 to about 5xc3x971015 atoms/cm2 and energies of from about 20 to about 60 KeV; step (h) comprises etching the first sidewall spacer with dilute aqueous HF, e.g., 1:100 HF/H2O at about 20-35xc2x0 C.; step (i) comprises rapid thermal annealing to diffuse and activate the second conductivity type dopant impurities introduced during step (g) to form the pair of heavily-doped source/drain regions; step (j) comprises selectively implanting dopant ions of second conductivity type at dosages of from about 5xc3x971013 to about 5xc3x971014 atoms/cm2 and energies of from about 5 to about 30 KeV; and step (k) comprises rapid thermal annealing to diffuse and activate the second conductivity type dopant impurities introduced during step (j) to form the shallow-depth, lightly- or moderately-doped source/drain extension.
According to a further embodiment of the present invention, the method comprises forming a relatively narrow sidewall spacer on each of the first and second opposing side surfaces of the layer stack prior to performing step (b), the relatively narrow sidewall spacers comprising an etch resistant material which is retained throughout processing, and selected from silicon oxides, silicon nitrides, and silicon oxynitrides.
According to another aspect of the present invention, a method of manufacturing an asymmetrically-configured silicon-based MOS-type transistor is provided, which method comprises the sequential steps of:
(a) providing a MOS transistor precursor structure comprising a silicon semiconductor wafer substrate of a first conductivity type and a layer stack formed on a portion of a surface of the wafer, the layer stack comprising:
i. a thin gate insulating layer comprising a silicon oxide layer about 25-50 xc3x85 thick in contact with the wafer surface; and
ii. a gate electrode layer comprising heavily-doped polysilicon formed on the gate insulating layer, the layer stack comprising first and second opposing side surfaces and a top surface;
(b) forming first and second, relatively narrow insulative, tapered sidewall spacers on respective ones of said first and second opposing side surfaces, said first and second relatively narrow sidewall spacers comprising a first, relatively etch-resistant dielectric material selected from silicon oxides, silicon nitrides, and silicon oxynitrides;
(c) forming first and second relatively wide, insulative, tapered sidewall spacers on respective ones of the first and second sidewall spacers, the first and second relatively wide sidewall spacers comprising a second dielectric material comprising a UV-nitride having an as-deposited etch resistance;
(d) selectively positioning a masking material over the sidewall spacers on the first opposing side surface of the layer stack;
(e) selectively implanting the exposed second, relatively wide sidewall spacer on the second opposing sidewall surface of the layer stack with impurities for reducing the etch resistance from its as-deposited state to a more readily-etchable state;
(f) removing the masking material from over the sidewall spacers on the first opposing side surface of the layer stack;
(g) selectively removing the reduced etching resistance, second relatively wide sidewall spacer layer by etching with dilute aqueous HF;
(h) selectively implanting dopant impurities of a second, opposite conductivity type into exposed portions of the substrate surface adjacent the first relatively wide sidewall spacer and adjacent the second relatively narrow sidewall spacer to form a pair of spaced-apart, heavily-doped implants in the wafer;
(i) removing the first relatively wide sidewall spacer by an etching process with dilute aqueous HF;
(j) performing rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (h), thereby forming a pair of heavily-doped source/drain regions in the wafer substrate, each having a junction therewith at a predetermined depth below the wafer surface, a first one of the pair of heavily-doped source/drain regions being laterally spaced away from a respective proximal edge of the gate insulating layer by a distance substantially equal to the width of the lower end of the relatively wide sidewall spacer adjacent the wafer surface and a second one of the pair of heavily-doped source/drain regions extending to just beneath a respective proximal edge of the gate insulating layer;
(k) selectively implanting second, opposite conductivity type dopant impurities into the exposed portion of the wafer surface intermediate the gate insulating layer and the first, laterally spaced-away, heavily-doped source/drain region to form a lightly- or moderately-doped extension region; and
(l) performing rapid thermal annealing to diffuse and activate the dopant impurities implanted in step (k), thereby forming a shallow-depth, lightly- or moderately-doped source/drain extension extending from the proximal edge of the first, laterally spaced-away, heavily-doped source/drain region to just beneath the respective proximal edge of the gate insulating layer.
According to yet another aspect of the present invention, silicon-based, asymmetrically-configured MOS-type transistor devices formed by the method of the above-enumerated steps (a)-(l) are provided.
According to still another aspect of the present invention, an asymmetrically-configured MOS-type transistor device comprises:
(a) a semiconductor substrate of one conductivity type and having a surface;
(b) a layer stack formed on a portion of the surface, the layer stack comprising:
i. a thin gate insulating layer in contact with the substrate surface; and
ii. a gate electrode layer formed on the gate insulating layer; and
(c) a pair of source and drain regions of opposite conductivity type formed within the substrate and extending to just beneath opposite edges of the gate insulating layer, wherein:
i. a first one of the pair of source and drain regions comprises a first, heavily-doped portion laterally spaced away from the respective proximal edge of the gate insulating layer and having a relatively deep junction depth, and a second, shallow-depth, moderately or lightly-doped extension portion extending from the proximal edge of the first portion to just beneath the respective proximal edge of the gate insulating layer; and
ii. a second one of the pair of source and drain regions comprises a heavily-doped, relatively deep junction depth portion extending to just beneath the respective proximal edge of the gate insulating layer.
In embodiments according to the invention, the semiconductor substrate comprises a monocrystalline silicon wafer of p or n first conductivity type, the thin gate insulating layer comprises a silicon oxide layer about 25-50 xc3x85 thick, and the gate electrode layer comprises heavily-doped polysilicon; and the first one the pair of source and drain regions comprises a source region and the second one of the pair of source and drain regions comprises a drain region, or alternatively, the first one of the pair of source and drain regions comprises a drain region and the second one of the pair of source and drain regions comprises a source region.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.